Meta has partnered with AMD to showcase a form of memory that can perchance perchance be added onto servers using compute categorical hyperlink (CXL) technology.
The use of this open popular for a excessive-sail processor-to-tool and processor-to-memory interface, CXL memory can lead to a long way extra efficient use of memory, saving hyperscalers money whereas boosting performance.
The demo board, which integrated an AMD EPYC 9004 Genoa processor, had four dual in-line memory module (DIMM) slots surrounding it, alongside a heat sink and fan. It also had a PCIe x16 connector, in accordance to Aid the Dwelling.
Ushering the age of CXL 2.0 memory
The CXL 2.0 memory growth demo on the Open Compute Project (OCP) Global Summit 2023 became irregular in that it became built round an AMD chip, in tell of Intel’s Xeon chip built on the Sapphire Rapids architecture.
One of many vital promises of CXL memory is the likelihood it’ll give hyperscalers to reuse DRAM, with memory controllers that can interface between DDR4 or DDR5 RAM and CXL possibly leading to predominant label savings.
Basically, as DDR4 memory begins to be phased out for DDR5 RAM, this can also incur a serious label investment for hyperscalers in managing their recordsdata centers. In fact, it’s maybe one of possibly the most critical costs here.
The use of CXL memory will doubtless be a capability for these companies to proceed using any DDR4 RAM units they prefer to share out, as add-on memory to elevate more recent units and improve their server configurations.
There are several configurations of CXL memory in enhance, with Aid the Dwelling also reporting on the aforementioned Intel chip being showcased alongside the Astera Labs CXL memory growth card at SC22.
FADU, final month, also showcased a tool that can perchance perchance elevate a server with additional memory over CXL 2.0. Its Apollo CXL 20 switch became built to slash latency and power consumption whereas being outdated-long-established.
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